The most advanced manufacturing processes require various technical supports, and wiring is a crucial part.
Applied Materials announced the launch of innovative material engineering technology, which improves the power efficiency of computer systems by enabling the miniaturization of copper wiring to 2nm and below logic nodes. TSMC and Samsung Semiconductor are actively adopting it.
Applied Materials pointed out that it has launched an upgraded version of Black Diamond, the latest product in the company's Producer Black Diamond PECVD series. This new material reduces the smallest k value, advances miniaturization to 2nm and below, and provides higher mechanical structural strength, which is crucial for chip manufacturers and system companies to upgrade 3D logic and memory stacking to new heights.
Dr. Prabu Raja, President of Applied Materials' Semiconductor Products Business Group, said: "The AI era requires more energy-efficient computing, where chip wiring and stacking are crucial for performance and energy consumption. Applied Materials' latest integrated material solution enables the industry to miniaturize low-resistance copper wiring to emerging angstrom nodes, and our most advanced low-dielectric constant materials reduce capacitive effects and strengthen chip structural strength, elevating 3D stacking to new heights."
Beyond the physical challenges of classical Moore's Law miniaturization
At present, the most advanced logic chips can contain tens of billions of transistors, connected by miniature copper wires with a total length of over 96.5 kilometers. Each layer of chip wiring starts with a thin film of dielectric material, which is etched to form channels filled with copper. For decades, low dielectric constant and copper have been the main wiring combination in the industry, and chip manufacturers have been able to achieve improvements in miniaturization, performance, and power efficiency in each generation of products.The latest Black Diamond technology is being adopted by all leading logic and DRAM chip manufacturers.
New binary metal liners enable ultra-fine copper wiring
To scale down chip wiring, chip manufacturers etch each layer of low-k dielectric film to form trenches, then deposit a barrier layer to prevent copper migration into the chip, which would cause yield issues. Subsequently, a liner is applied on the barrier layer to ensure adhesion during the final copper reflow deposition process, slowly filling the remaining volume with copper.
Customer Evaluation
Samsung Electronics Vice President and Head of the Foundry Development Team, Sunjung Kim, said: "As the progress of patterning technology drives the miniaturization of device sizes, other areas including the resistance, capacitance, and reliability of interconnect power grid wiring still pose key challenges. To help overcome these challenges, Samsung is adopting various material engineering innovations to extend the benefits of scaling to the most advanced nodes."
TSMC Executive Deputy General Manager and Co-Chief Operating Officer Dr. YJ Mii said: "The semiconductor industry must significantly improve energy efficiency to achieve sustainable growth in AI computing. New materials that reduce interconnect resistance will play a key role in the semiconductor industry, along with other innovations to refine the overall system performance and power."
Growing wiring business opportunitiesApplied Materials mentioned that as an industry leader in chip wiring process technology, from the 7nm to 3nm node, the interconnect wiring steps have approximately tripled, increasing the market opportunity for Applied Materials in the wiring field by more than $1 billion, with a greenfield capacity of 100,000 wafers per month (WSPM), which is about $6 billion. Looking ahead, the introduction of Backside Power Delivery Network (BSPDN) technology is expected to increase Applied Materials' wiring business opportunities by another $1 billion, reaching about $7 billion per 100,000 wafers.
TSMC, Samsung, Intel, and other major wafer manufacturers are actively deploying backside power supply network technology and will incorporate it into the development blueprint of cutting-edge logic processes. According to a report by South Korean media The Elec, following Intel's announcement of its "PowerVia" backside power supply technology to be integrated into the Intel 20A process technology, Samsung Electronics also announced its research results of backside power supply technology at the previous VLSI conference in Japan, which will also be used for its 2nm process technology.
Over the past years, chips have been manufactured layer by layer from the bottom up, similar to pizza. Chip manufacturing starts with the smallest component - transistors, and then increasingly smaller wiring layers are built to connect the transistors with metal layers. These wires are called signal interconnects, which also include power lines to supply power to the transistors. After the chip die is manufactured, it still needs to be flipped and packaged. Packaging mainly protects the die and provides an interface with the outside world, making it a truly commercial chip.
However, as transistors become smaller and denser, the wiring layers where interconnects and power lines coexist have become an increasingly chaotic network, with more and more stack layers, which may require passing through 10 to 20 layers of stacks to provide power and data signals to the transistors below.
In response to this, leading chip manufacturers are striving to research backside power supply technology, that is, looking for ways to move power lines to the back of the chip, so that the front side of the chip only needs to focus on signal interconnects with the transistors. That is to say, the manufacturing of the wafer will first manufacture the front side transistors, then add the interconnect layer, then flip the wafer, and then grind and thin the back side. Through the Through-Silicon Vias (TSV) technology, the power supply network is manufactured on the back side of the wafer and connected with the embedded power rails.
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