More and more players are entering the FOPLP market. NVIDIA, Apple, TSMC and other leading manufacturers are actively investing in the fan-out packaging field, triggering huge market opportunities. TrendForce's latest report yesterday (3) pointed out that the currently highly anticipated panel-level fan-out packaging technology (FOPLP) will be first applied to consumer ICs, and will enter mass production as early as the second half of this year; as for AI chips, it will not be until 2027 to 2028. According to TrendForce's forecast, the Taiwanese manufacturer that will grab the panel-level fan-out packaging business the fastest is Innolux. Innolux has made great progress in the panel-level fan-out packaging business and has won orders from two major European leading manufacturers, NXP and STMicroelectronics, locking in the automotive and power management IC fields. At this stage, the production capacity is fully loaded, and mass production shipments are planned for this quarter, and the second phase of the expansion plan has been initiated. TrendForce pointed out that after TSMC developed the wafer-level fan-out packaging (FOWLP) technology named InFO (Integrated Fan-Out Packaging) in 2016 and applied it to the A10 processor used in the iPhone 7, packaging and testing factories also successively developed wafer-level fan-out packaging technology. As AI chips require a larger area, fan-out packaging has become more popular, and panel-level fan-out packaging technology with glass as the substrate has also become popular. Since the second quarter, chip manufacturers such as AMD have actively contacted TSMC and packaging and testing factories to discuss chip packaging using panel-level fan-out packaging technology, which has led the industry to pay more attention to related technologies. From the perspective of TSMC, it is rumored that it is working with equipment and raw material suppliers to develop new advanced chip packaging technology, using a substrate similar to a rectangular panel for packaging to replace traditional circular wafers, so that more chipsets can be placed on a single wafer. TSMC previously responded that the company will closely monitor the progress and development of advanced packaging technology, including panel-level packaging technology. FOPLP Introduces AI GPU, Mass Production Expected by 2027
TrendForce Technology analysis indicates that there are currently three main application modes for FOPLP technology. First, OSAT (Outsourced Semiconductor Assembly and Test) manufacturers are transitioning the packaging of consumer ICs from traditional methods to FOPLP. Second, wafer foundries and OSAT manufacturers are shifting the 2.5D packaging of AI GPUs from wafer-level to panel-level. Additionally, panel manufacturers are expanding into the consumer IC packaging sector; all segments of the industry chain are actively deploying FOPLP technology.
Further analysis of industry cooperation cases reveals that AMD's discussions with Powertech and ASE on PC CPU products and Qualcomm's discussions with ASE on PMIC products have made significant progress. TrendForce Technology discloses that due to the line width and spacing of FOPLP not yet reaching the level of FOWLP, applications are temporarily halted.
In terms of AI GPU packaging, major manufacturers such as AMD and NVIDIA are the most active, discussing related products with TSMC and SPIL. Both parties are collaborating to transition the 2.5D packaging model from wafer-level to panel-level, further increasing chip packaging size and reducing unit costs. However, due to technical challenges, industry players are still in the evaluation phase for this transition.
Industry insiders state that the rectangular substrate is a change from the traditional round silicon interposer to a larger rectangular substrate, which does not mean completely replacing round wafers but using rectangular substrates during the packaging stage to improve area utilization. This technology also belongs to 2.5D packaging, aiming to enhance component transfer efficiency and reduce costs to accommodate more chip combinations, which is beneficial for the wiring arrangement of large AI chips.
The advantages and disadvantages of FOPLP technology, as well as the incentives and challenges for adoption, coexist. TrendForce Technology believes that the main advantages are low unit costs and large packaging sizes. However, the technology and equipment systems still need development, and the commercialization process of the technology has a high degree of uncertainty. It is estimated that the development of FOPLP packaging technology in consumer IC and AI GPU applications may be mass-produced between the second half of 2024 and 2026, and between 2027 and 2028.
Differences between Panel-Level Packaging, Wafer-Level, and Traditional Packaging
Fan-out wafer-level packaging (FOWLP; Fan-out Wafer Level Packaging) is generally defined as performing most or all of the packaging and testing procedures directly on the wafer, followed by cutting to create individual components. Compared to traditional packaging, it provides a smaller packaging size and improves thermal performance and other capabilities. However, due to the high cost of equipment, it also causes limitations in chip manufacturing size (shape mismatch leading to waste), which is why the final panel-level technology has developed.
The biggest change in fan-out panel-level packaging (FOPLP; Fan-out Panel Level Packaging) is the shift from the original process to directly using "glass material" as the substrate, which can accommodate more I/O numbers, has stronger performance, and saves power consumption. This technology is also the glass substrate technology that NVIDIA and AMD previously considered introducing. However, different industries have different packaging technologies, so no further details are provided.According to the previous explanation by the panel giant Innolux, taking a 12-inch wafer as an example, the area of Innolux's FOPLP production line is 700x700mm, which is approximately equivalent to 6.9 12-inch wafers, surpassing the area of a single 12-inch wafer at 706.5 mm² of FOWLP. Not only will the future output far exceed that of traditional and wafer-level packaging, but the cost will also decrease significantly.
However, NVIDIA has been rumored to be introducing panel-level packaging technology as soon as possible. Many people think that the current severe shortage of production capacity, coupled with the industry's huge demand for the dominant position of CoWoS advanced packaging technology, will it be challenged? The answer is "not impossible." Panel-level packaging technology is not only looking at efficient production capacity, but the glass substrate is also one of the important reasons for AI chips to continue Moore's Law, which CoWoS does not have.
Of course, the CoWoS technology is unique to TSMC, with patents and technology in the hands of TSMC. Coupled with the one-stop wafer foundry and packaging, it is difficult for other factories to compete with it. Moreover, the glass substrate and panel-level packaging technology are still a long way from mass production, and it is not easy to determine who will win or lose just by looking at the technical aspects.
In addition, according to descriptions from factories such as Innolux, the current panel-level packaging production line chips are mostly used in fields such as the Internet of Things and automotive chips, and have not been used in the packaging process of AI computing chips or server processors in the past. There are still many technical limitations to be broken through. However, many AI giants including NVIDIA, AMD, and Intel have announced their commitment to layout, and future business opportunities are expected.
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