Mechanical stress increases with size enlargement and material heterogeneity.
Warpage has become an increasingly serious concern in advanced packaging, where the heterogeneous mixture of materials may lead to uneven stress points during assembly and packaging processes, as well as under real loads in the field.
Warpage plays a key role in determining whether advanced packaging can be successfully assembled and meet long-term reliability goals. New advancements, such as packaging compounds with improved thermal performance, advanced modeling techniques, and innovative architectures involving two packaging steps, are making the control of packaging warpage more stringent, while also providing more flexibility for optimizing a robust multichip system.
Warpage is an inevitable result of the mismatch in the coefficients of thermal expansion (CTE) between silicon chips, packaging compounds, copper, polyimide, and other materials. It changes throughout the assembly process and can lead to delamination or cracking failures. The most vulnerable points include low-k cores, which are susceptible to cracking and short-circuiting, or non-wetting failures of microbumps.
"A very hot topic right now is about warpage and stress in packaging," said Kenneth Larsen, Senior Director of Product Management at Synopsys. "It's not just during the manufacturing process when you change the temperature. That can cause warpage. But you may also encounter warpage issues when you need to insert the device being built into a socket."
Even if warpage issues are effectively addressed during assembly and packaging processes, devices may still warp under heavy loads in the field. This is especially true in heterogeneous designs, where chips are developed using different materials or processes, and logic is concentrated in specific areas of asymmetric packaging.The shift towards multi-chip packaging is rapidly accelerating due to the increasing demand for higher processing speeds and low latency, especially in mobile, automotive, and high-performance computing/AI applications. Engineers are increasingly turning to modeling and simulation to understand temperature-dependent warpage, which can vary depending on chip thickness, the ratio of mold to silicon, and the type of substrate. Organic substrates are very attractive because they are cost-effective and can be customized to any size, but they are more flexible and more prone to warping than silicon substrates.
All these considerations point to the need for thermal and structural models of complex heterogeneous assembly and packaging. "Advanced modeling allows companies to simulate the behavior of different materials, thermodynamics, and mechanical stresses during the assembly process," said Mike Kelly, Vice President of Amkor Chip/FCBGA Integration. "Through this virtual experimentation, potential challenges can be predicted and mitigated, ensuring that the final product meets strict quality and reliability standards."
How warpage occurs
The assembly process involves multiple heating and cooling steps, which can cause a certain degree of deformation between adjacent materials with different thermal and mechanical properties. In advanced packaging, warpage within the 100-micron range is not uncommon.
Warpage has become one of today's issues because the chip size is large, and the process window for chips, redistribution layers (RDL), substrates, and various sizes of bumps is very tight. The relative expansion and contraction of adjacent materials depend on the difference in the CTE (coefficient of thermal expansion) of the materials, which indicates the increase in size (ppm/°C) for each degree of temperature change.
"Chips are usually relatively large chips," said Dick Otte, CEO of Promex Industries. "In an iPad, it's 20 x 30 millimeters, with up to 10,000 I/Os - usually copper pillars. Just placing a single chip on a substrate can be a considerable challenge because the pitch is very small. So for these packages, controlling warpage and flatness is crucial. It needs to remain flat throughout the entire reflow soldering process to bridge the gap between the copper pillars and the contact points on the circuit board without warping."
Warpage can occur upwards, with edges bending, or downwards, depending on the relative CTE of the materials in the stacked materials. For example, silicon is 2.8; copper is 17; FR4 PCB is 14 to 17 ppm/°C. The most significant difference in CTE is between silicon interposers and organic substrates.
It is helpful to imagine the stacks in the package as groups of materials. "You have to look at the CTE of the materials and how they react to temperature, so you have relatively low-expansion copper at the top and solder at the bottom," said Otte. "They have a high-expansion dielectric in the middle, so when you heat this thing, it expands by the same amount. If you just put all the copper on top, when you heat it, this thing will warp towards the copper side. Copper is 15 ppm per degree Celsius. Organics are more like double, 25 to 30 ppm/°C."
Other key indicators are modulus, which is the elasticity of the material, and the glass transition temperature (Tg), which is the temperature at which the material begins to flow. These values are also relevant. For example, when it comes to the thermal behavior of polymers like epoxy molding compounds (EMC), the modulus tends to drop sharply above their glass transition temperature. This is because polymer chains tend to slide freely in a liquid state and are harder in a solid state.Besides reflow soldering, warpage is also prone to occur during the curing process after molding. Hung-Chun Yang of ASE and his colleagues recently determined that the thickness of the chip significantly affects the level of warpage measured in multiple steps in the existing chip first fan-out packaging process. They pointed out that "severe wafer warpage occurs after curing, leading to difficulties in alignment and processing in subsequent processes." To reduce packaging warpage, the team replaced the metal carrier/film method with a glass carrier. The team also determined that the three-dimensional finite element method (FEM) can capture warpage behavior and matches well with actual test vehicle data.
The chip first process first probes the manufactured wafer, then thins it and electroplates copper pillars before sawing. The initial process uses a metal carrier that is removed after molding, and a film is used as a substitute. The improved process uses a glass carrier that goes through molding, curing, mold grinding, RDL, and copper pillar processes, and then debonding.
Warpage reaches the maximum level during the post-molding curing, and the change is most significant after the curing step and the debonding of the glass carrier. The overall flow of the glass carrier reduces warpage. In addition, ASE engineers determined that by increasing the wafer thickness from 0.54mm to 0.7mm, an additional 35% warpage reduction can be achieved.
The second strategy for reducing warpage involves using EMCs with different thermal properties, especially when the process requires two molding steps. Amkor engineers recently evaluated the reliability performance of two high-performance multi-chip packages by modeling and manufacturing two high-performance test vehicles. One of the modules is about the size of a mesh board, containing 1 ASIC, 2 HBMs, and 2 bridging chips (33 x 26mm). The second module is the size of three mesh boards, with 2 ASICs, 8 HBMs, and 10 bridging chips (54 x 46mm). Heejun Jang and his colleagues from Amkor Technology Korea used the Ansys Parametric Design Language (APDL) version 16.1 simulator for modeling and simulation, and compared the results with test vehicles containing virtual chips.
Amkor's final chip S-Connect process starts with a carrier wafer, on which the copper pillars and pillars of the bridging chips are manufactured (see Figure 2). Integrated passive components and bridging chips are embedded in the first mold, which is ground back after curing. RDL and pads are deposited on the mold, and the chips are connected to the pads using micro-bumps. Then, the solder is reflowed and underfilled. The second mold cures and is ground back around the chips facing up, and C4 bumps are made on the bottom for flip-chip connection to the substrate. Simulation analyzed the warpage of nine combinations, which are composed of three different EMCs with high, medium, and low CTE (7 to 12 ppm below Tg, 22 to 46 ppm above Tg) and high to low glass transition temperature (145°C to 175°C).
Warpage as a function of EMC selection shows that all materials follow the same smile pattern at room temperature and the cry pattern at high temperatures (250°C). EMC with a lower CTE causes less warpage. The warpage level is more obvious when the mold occupies a larger area relative to the chip area. More importantly, the warpage level of the 450µm chip is about 50% higher than that of the 650µm thick chip. Interestingly, the thicker silicon chips are three times more effective than the EMC material selection in controlling the overall module warpage, so chip thickness is the biggest lever for reducing warpage, if possible.
Amkor conducted moisture resistance tests, highly accelerated stress tests, thermal cycling conditions B, and high-temperature storage tests on its advanced packaging test vehicles. These tests require the eradication of early failure issues, and cross-sectional analysis can reveal any cracks or potential defects that may lead to failures in actual use.
Although the above examples may constitute most of today's chip packaging, the packaging size is still growing, which means more attention needs to be paid to warpage. This will increasingly drive the assembly line towards the development of digital twins or virtual representations to achieve process and packaging optimization."By creating a virtual representation of the semiconductor assembly line, potential areas of concern can be identified and control strategies can be optimized," says Kelly of Amkor. "Virtual manufacturing in packaging assembly allows companies to assess the impact of design changes on the manufacturing process before creating physical prototypes. This not only accelerates the product development cycle but also minimizes the risk of costly mistakes."
Early identification of potential bottlenecks further shortens cycle time and improves overall efficiency.
Conclusion
Looking ahead, teams composed of designers and packaging engineers will need to pay more attention to mechanical and thermal performance. "The tight tolerance requirements in new packaging designs necessitate accurate analysis of mechanical and electrical tolerances during the stacking process," says Curtis Zwenger, Vice President of Engineering and Technical Marketing at Amkor. "A higher level of process capability is needed, with common metrics such as CpK. Through this modeling, these critical interactions can be identified early in the process development. In turn, these analyses guide investments in advanced process control to ensure process capability is maintained."
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