The MDI (Multi-Chip Integration) alliance initiated by Samsung Electronics in June last year is now attracting more collaborators. Currently, the number of partners in the alliance, including several memory, packaging substrate, and testing manufacturers, has increased to 30, up from 20 last year, adding 10 in just one year.
In recent years, with the surge of AI, the rise of advanced packaging has gradually become a consensus in the industry. When the demand for computing power and the number of transistors that circuits can accommodate are both approaching their limits, stacking and combining different chips are considered to be a more efficient chip manufacturing concept.
The increase in the number of partners also reflects Samsung Electronics' proactive attitude and firm determination in semiconductor packaging technology. By establishing close cooperation with more partners, Samsung Electronics can better integrate resources, enhance technical strength, accelerate product development and market promotion. At the same time, this will also help Samsung Electronics to achieve greater breakthroughs and progress in the field of semiconductor packaging technology.
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TSMC and Samsung successively established two major advanced packaging alliances
3DFabric Alliance
At the Open Innovation Platform Ecosystem Forum in 2022, TSMC announced the establishment of the Open Innovation Platform (OIP) 3D Fabric Alliance.
Members of the 3DFabric Alliance can obtain TSMC's 3DFabric technology early, enabling them to develop and optimize solutions in sync with TSMC, and also allowing customers to take a leading position in product development, and to obtain the highest quality and existing solutions and services from EDA and IP to DCA / VCA, memory, outsourced packaging testing (OSAT), substrate, and testing. This alliance is TSMC's sixth Open Innovation Platform (OIP) alliance.
TSMC's 3DFabric technology includes front-end 3D chip stacking or TSMC-SoIC (System-on-Integrated-Chip), as well as back-end technologies including CoWoS and InFO series packaging technologies, which can achieve better performance, power consumption, size, appearance, and functionality, achieving system-level integration.In addition to the already mass-produced CoWoS and InFO, TSMC began manufacturing System-on-Integrated-Chips (SoIC) in 2022. TSMC currently has the world's first fully automated 3DFabric wafer factory in Zhunan, integrating advanced testing, TSMC's SoIC, and InFO operations, providing customers with the best flexibility, optimizing packaging with better production cycle times and quality control.
MDI Consortium
Coincidentally, on June 27 last year, at the 7th Samsung Foundry Forum (SFF), Samsung announced the latest roadmap for chip manufacturing processes and business strategies, and established the Multi-Die Integration (MDI) Consortium. Currently, the consortium has grown to include 30 partners, including memory, packaging substrate, and testing manufacturers.
The MDI Consortium mainly focuses on 2.5D and 3D heterogeneous integrated packaging technologies, which aim to integrate multiple bare chips, such as CPUs, GPUs, HBM (High Bandwidth Memory), etc., into a single package to meet the growing demand in the high-performance computing (HPC) field. As the scale of transistor miniaturization has approached its limits, the industry generally believes that stacking different small chips is a more efficient approach. Therefore, the establishment and development of the MDI Consortium are of great significance to Samsung Electronics in the field of semiconductor packaging technology.
Some industry insiders commented: "Samsung Electronics is trying to break TSMC's market advantage through heterogeneous integrated packaging technologies like i-Cube, but TSMC's reliability and technical strength should not be underestimated. Samsung Foundry can only catch up by accepting an open ecosystem like the MDI Consortium."
CPUs and GPUs adopt different design concepts in the manufacturing process. Although Samsung Electronics has the advantage of offering "one-stop" solutions for foundry, HBM, and packaging, it still needs the support of design, post-processing companies, and EDA tool companies.
As the world's largest foundry chip manufacturer, TSMC has always been at the forefront in the field of advanced packaging technology. Samsung's establishment of the MDI Consortium aims to narrow the gap with TSMC in packaging technology by strengthening R&D and application in the field of 2.5D and 3D packaging technologies. Through close cooperation with more partners, Samsung can share technical resources, reduce R&D costs, and accelerate product launch times.
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Advanced Packaging Gradually Becomes Industry Consensus
In 2008, TSMC began to layout advanced packaging, first establishing an integrated interconnection and packaging technology integration department. In 2009, it started strategic layout of three-dimensional integrated circuit system integration platforms, building four advanced packaging and testing factories in Hsinchu, Tainan, Taoyuan, and Taichung, which laid the foundation for its subsequent development of advanced packaging technology.In 2010, TSMC began the development of 2.5D Interposer technology. The following year, they introduced the 2.5D Interposer technology CoWoS (Chip on Wafer on Substrate). The first generation of CoWoS utilized a 65-nanometer process, with line widths reaching 0.25 µm, achieving 4 layers of wiring, providing a solution for the integration of high-performance products such as FPGAs and GPUs. The "Virtex-7 2000T FPGA" model from Xilinx is one of the most representative CoWoS products. Currently, CoWoS has received high-end HPC chip orders from Xilinx, Nvidia, AMD, Fujitsu, Google, and others.
In the third quarter of 2019, the CoWoS technology had been expanded to 7 nanometers, capable of heterogeneously integrating multiple 7-nanometer system monolithic chips with the second-generation high bandwidth memory (High Bandwidth Memory 2, HBM2) on a silicon interposer substrate of double the size of a photomask.
In 2020, TSMC announced the 3D Fabric advanced packaging technology series, including 2D and 3D front-end and back-end interconnection technologies. The front-end technology TSMC-SoIC (System on Integrated Chip) uses what is required for 3D silicon stacking, including CoW and WoW stacking technologies; the back-end process includes packaging technologies such as CoWoS (Chip on Wafer on Substrate, wafer-level packaging) and the InFO series.
TSMC's CoWoS, InFO, SoIC, and other packaging technologies can perform wafer-level bonding technology for processes of 10 nanometers or below, greatly enhancing TSMC's competitiveness in advanced process technologies. TSMC hopes to leverage the advantages of heterogeneous integration to increase the number of transistors in the system by 5 times or more. In 2023, TSMC announced the official launch of the Advanced Backend Fab 6, adopting 3DFabric technology, preparing for the mass production of system integration technology.
In the field of advanced packaging technology, Samsung is not far behind and has always maintained an active R&D attitude.
After losing the Apple order in 2015, Samsung began to increase its R&D efforts in advanced packaging technology, especially the FOPLP technology. In 2018, the FOPLP technology was commercialized and successfully applied to the processor packaging application of the Galaxy Watch.
In 2018, Samsung Electronics' 3D packaging technology "X-Cube" was completed. Unlike the previous parallel packaging of multiple chips, the brand-new X-Cube 3D packaging allows for the stacking of multiple chips, making the finished chip structure more compact. The communication connection between chips uses TSV technology instead of traditional wires. According to Samsung, the technology can now stack SRAM memory chips on top of the main chip to free up more space for stacking other components. The technology can now be used for product lines with 7nm or even 5nm process technology, which means it is very close to mass production.
In August 2020, Samsung announced the launch of the 3D advanced packaging technology "X-Cube". This technology is based on TSV silicon through-hole technology, which can vertically stack different chips, releasing space to stack more memory chips. X-Cube technology can already be used for 7nm and 5nm processes, meeting the performance requirements of fields such as 5G, AI, AR, VR, HPC, and mobile chips.
In May 2021, Samsung announced that its next-generation 2.5D packaging technology "I-Cube4" is about to hit the market. "I-Cube4" stands for "Interposer-Cube4". As a 2.5D packaging technology brand of Samsung, it is a new generation of packaging technology that uses a silicon interposer method to arrange and package multiple chips on a single chip. The technology integrates one logic chip and four high-bandwidth memories (HBM), greatly improving the communication efficiency between logic devices and memory. Although some experts have pointed out that the technology has parasitic parameter defects and is too thin, Samsung continues to optimize and improve.
In addition, Samsung also launched its 2.5D packaging solution H-Cube in 2021. This solution further achieves a larger 2.5D packaging by integrating two substrates with different characteristics, including a refined ABF (Ajinomoto Build-up Film) substrate and an HDI (High Density Interconnection, high-density interconnection) substrate.In order to compete with TSMC, Samsung plans to launch its advanced 3D chip packaging technology, SAINT (Samsung Advanced Interconnection Technology), in 2024. This technology will integrate memory and processors of high-performance chips such as AI chips in a smaller package size. Samsung's SAINT will be used to formulate various solutions, offering three types of packaging technologies. One of the branches of Samsung Electronics' next-generation 3D chip stacking technology, SAINT-D, is currently in the concept verification stage and is about to be launched in chip form, achieving vertical integration of HBM memory.
Samsung Electronics also plans to launch a brand-new integrated AI solution with CPO (Co-Packaged Optics) in 2027, aiming to provide customers with high-speed, low-power interconnection options.
In addition, Samsung also plans to integrate its storage chips, foundry, and chip packaging services to provide customers with a one-stop solution to manufacture their artificial intelligence (AI) chips more quickly and ride the AI wave.
According to data from Market.us, the global Chiplet market size is expected to grow from $3.1 billion in 2023 to about $107 billion in 2033, with a compound annual growth rate of 42.5% during the forecast period from 2024 to 2033.
More and more enterprises, research institutions, and industry associations are beginning to pay attention to the development and application of advanced packaging technologies. Advanced packaging technology has become an important force driving the continuous development of the electronics industry. The rapid growth of the market size, the gradual formation of industry consensus, and the optimistic investment prospects all indicate that advanced packaging is gradually becoming an industry consensus.
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Wafer factories compete for advanced packaging, and the "mid-road" concept is hot
In the process of evolving from traditional packaging technology to advanced packaging, the concept of "mid-road process" has been proposed, which gradually blurs the boundary between the front-end wafer manufacturing process and the back-end packaging process. After TSMC divided its packaging platform "3DFabric" into "front-end" and "back-end" packaging technologies, this division will further break the boundary between wafer manufacturing and packaging, which will have a new impact on the original design, manufacturing, and testing产业结构.
In recent years, with the explosion of AI, the rise of advanced packaging has gradually become an industry consensus. When the demand for computing power and the number of transistors that circuits can accommodate are both approaching their limits, stacking and combining different chips are considered to be a more efficient chip manufacturing concept. Advanced packaging technology is the key technology to extract the maximum power from the latest chip designs, which is crucial for chip foundries to compete for business. This has also led to wafer factories beginning to get involved in advanced packaging technology.
As an IDM and wafer foundry giant, Intel is also actively deploying 2.5D/3D packaging, challenging TSMC.
(Note: The term "产业结构" was left untranslated as it seems to be incomplete and may refer to "industrial structure" or "structure of the industry" depending on the context.)Through years of technological exploration, Intel has successively launched various advanced packaging technologies such as EMIB, Foveros, and Co-EMIB, striving to achieve the goal of doubling interconnect bandwidth and halving power consumption through 2.5D, 3D, and embedded heterogeneous integration forms.
EMIB is Intel's attempt in 2.5D IC, with the full name being "Embedded Multi-Die Interconnect Bridge". It does not introduce an additional silicon interposer, but only adds a silicon bridge layer (Silicon Bridge) at the edge connection of two dies, and customizes the I/O pins on the edge of the dies to match the bridge standard.
In December 2018, Intel demonstrated a brand-new 3D packaging technology called "Foveros", which is another leap in advanced packaging technology following the breakthrough EMIB packaging technology launched by Intel in 2018.
In 2019, Intel introduced a new packaging technology called Co-EMIB, which is an innovative application combining EMIB and Foveros technologies. It allows two or more Foveros components to be interconnected, and basically achieves the performance level of a single chip.
In 2020, Intel demonstrated its new progress in the field of 3D packaging technology, which is called "Hybrid bonding" technology, aiming to replace the traditional "thermal compression bonding" technology, to achieve a bump pitch of 10 microns and below, providing higher interconnect density, bandwidth, and lower power consumption.
In the first half of this year, Morgan Stanley, an international investment bank, reported that the advanced packaging process used by Nvidia GB200 will use a glass substrate; in addition, Intel, Samsung, AMD, Apple, and other large manufacturers have previously stated that they will introduce or explore glass substrate chip packaging technology. This news has once again ignited the advanced packaging market.
TSMC has currently built six advanced packaging and testing factories. In response to the demand of many customers, TSMC began to urgently purchase equipment and configure capacity for CoWoS in the second quarter of 2023. At the end of 2023, TSMC's CoWoS monthly production capacity is about 15,000 wafers, and after additional equipment is added, the monthly production capacity is expected to reach more than 20,000, and will increase quarter by quarter.
Intel has currently built two advanced packaging factories in Oregon and New Mexico, USA, and announced in May 2021 to invest $3.5 billion to expand the advanced packaging capacity in New Mexico. In August 2023, it announced the establishment of a new advanced packaging factory in Penang, Malaysia, which is expected to be completed and put into operation by the end of 2024 to 2025. The factory will become Intel's largest 3D advanced packaging base. Intel plans to reach a 3DFoveros packaging capacity four times that of 2023 by 2025.
Samsung plans to build a new packaging line required for HBM in the Tianan factory area in South Korea in 2023, to supply high-performance chip manufacturers, and plans to increase the HBM production capacity to 2.5 times the current level by 2024. Samsung's HBM3 has passed the quality inspection of Nvidia and AMD and is about to become a supplier.
Intel, TSMC, and others are the main representatives of wafer factories, with more experience in the front-end manufacturing process, and can deeply develop TSV technology that requires etching and other front-end steps, thus being more advanced in 2.5D/3D packaging technology. Advanced packaging has become a key to semiconductor innovation, enhanced functionality, performance, and cost-effectiveness, and its process tends to be front-end, giving wafer foundries and IDM manufacturers a natural first-mover advantage in this field. At present, Sony, Powertech, Texas Instruments (TI), SK Hynix, UMC, and others are also actively deploying advanced packaging capacity, further intensifying the competitive landscape of the advanced packaging market.
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