In the field of chip manufacturing, the influence and dominance of advanced processes are growing increasingly significant, expanding from the previous logic chip foundry sector to the most advanced memory chip manufacturing. This is prominently reflected in TSMC and Samsung.
At present, TSMC's market dominance in 3nm process wafer foundry is evident, while Samsung is in a weaker position. For the upcoming 2nm process, Samsung must catch up quickly, or it will become increasingly difficult.
In the manufacturing of High Bandwidth Memory (HBM) chips, which were originally completed by the memory chip IDM giants themselves, the technical and manufacturing difficulties have increased significantly for the next generation HBM4, requiring more advanced process technologies to be involved.
01
Head-to-head competition in 2nm process technology
According to reports, TSMC will begin trial production of 2nm process technology chips in mid-July, earlier than the market's estimated fourth quarter.
TSMC's 2nm process will be the first to apply GAA (Gate-All-Around transistor) technology, which can provide better performance at a smaller process node.
According to TSMC, compared with the 3nm process, the 2nm process has a 10% to 15% improvement in energy efficiency and a 30% reduction in power consumption. When the trial production yield reaches a certain standard, it can be advanced to the mass production phase.
TSMC's 2nm process will include three versions: N2, N2P, and N2X. It is expected to start mass production of its first-generation GAA FET N2 node chips in the second half of 2025, and the next version, N2P, will be mass-produced by the end of 2026. These two versions of TSMC's 2nm process do not use backside power supply technology. However, the entire N2 series will add TSMC's new NanoFlex feature, which allows chip designers to match cells from different libraries (high-performance, low-power, different areas) in the same module to improve performance or reduce power consumption.Post-N2P will be the voltage-boosted N2X. Although TSMC had previously stated that N2P would add backside power supply technology in 2026, it seems that this is not the case; N2P will use conventional power supply circuits for reasons that are not yet clear.
There are reports that Apple has reached an exclusive agreement with TSMC to secure all of TSMC's initial 2nm process capacity.
According to foreign media reports, TSMC's capital expenditure in 2024 may reach the maximum value of $32 billion, and it is expected to further rise to $37 billion in 2025, mainly for the early deployment of 2nm process mass production and the purchase of advanced equipment. Currently, Samsung is also working hard on the 2nm process, and TSMC's purpose of deploying capacity in advance is to maintain its leadership in the wafer foundry field.
Reports earlier this year indicated that Samsung had already received a 2nm process chip order from the Japanese artificial intelligence (AI) startup Preferred Networks Inc. (PFN), thus gaining an advantage in the 2nm wafer foundry business.
On July 9, Samsung announced its cooperation with Preferred Networks Inc., offering a one-stop solution based on the 2nm process technology and 2.5D packaging technology Interposer-Cube S (I-Cube S) to manufacture AI chips for the other party.
Preferred Networks Inc. mainly engages in the development of artificial intelligence deep learning. It is reported that Samsung was chosen because it has both memory and wafer foundry services, with strong comprehensive capabilities and technical accumulation, and can provide a complete set of solutions for HBM design, production, and advanced packaging.
Samsung originally planned to mass-produce 2nm (SF2) process chips in 2025, and then adopt backside power supply technology in 2026. Compared with the 3nm process (SF3), Samsung's 2nm process has a performance increase of 12%, power efficiency increase of 25%, and area reduction of 5%.
TSMC and Samsung are competing in the mass production of 2nm process chips, and both parties also have issues that need to be resolved.
IBS estimates that compared with 3nm processors, the cost of 2nm chips will increase by about 50%.It is precisely due to the orders from major customers such as Apple, Nvidia, and AMD that TSMC (Taiwan Semiconductor Manufacturing Company) is able to make large-scale investments in the most advanced manufacturing processes. Otherwise, it would be difficult to sustain the expensive production lines like the 2nm process. Currently, TSMC is controlling costs in all aspects, including the expenditure on EUV (Extreme Ultraviolet) equipment and energy saving. Although other manufacturers will also face the cost issue of 2nm, Samsung and Intel seem to be less sensitive to costs in order to catch up with TSMC. In addition, TSMC's plan to build at least two advanced process wafer fabs in the United States has brought a lot of additional cost pressure. Therefore, TSMC's 2nm process production line must be carefully planned and managed.
For wafer foundries, yield is very important as it directly affects production costs and customer recognition.
Since entering the 5nm process era, yield has been the biggest problem faced by Samsung's wafer foundry business, especially at the 3nm process node. Samsung took the lead in introducing a brand new GAA (Gate-All-Around) transistor architecture, which is quite different from the FinFET transistors used before, and the manufacturing difficulty has increased significantly.
According to Notebookcheck, Samsung's 3nm process yield is hovering around 50%, and there are still some issues that need to be resolved.
In February of this year, according to South Korean media reports, there were major problems with Samsung's new 3nm process, and all trial production chips had defects, with a yield of 0%. The report pointed out that the Exynos 2500 chip using the 3nm process failed the quality test due to defects.
In order to catch up with TSMC, Samsung's 3nm process technology has adopted a more aggressive strategy, mainly reflected in the GAA transistor architecture. TSMC's 3nm still uses FinFET. The transition to GAA transistors will only happen at the 2nm process, and the aggressive result is that there will be some sacrifices in yield.
02
TSMC Dominates 3nm Foundry
It is understood that TSMC's 3nm process capacity has been booked by major customers until 2026.
The latest wave of orders is being competed for by MediaTek and Qualcomm. A new round of 5G smartphone flagship chip battles will start in the fourth quarter of this year, with MediaTek's Dimensity 9400 and Qualcomm's Snapdragon 8 Gen 4 facing off. The new processors from both manufacturers will be produced using TSMC's 3nm process, and they have recently entered the production phase, making the related capacity even more tight. This is because Nvidia, AMD, and Apple are actively striving for more TSMC 3nm capacity. It is reported that TSMC plans to triple its 3nm process capacity this year, but it is still in short supply.In order for the Tianji 9400 to be successfully launched, MediaTek is working hard to ensure the supply of 3nm process capacity. Currently, MediaTek's flagship Tianji 9300/9300+ chips are manufactured using TSMC's 4nm process.
Although Qualcomm has not yet announced the unveiling time and details of the new flagship chip Snapdragon 8 Gen 4, it is believed that this chip will also be produced using TSMC's 3nm process and will be launched in the fourth quarter, with an upgrade in chip performance. It is reported that Snapdragon 8 Gen 4 will be produced using TSMC's N3E process, with each chip priced at $220-240, which is 25%-30% higher than Snapdragon 8 Gen 3.
It is reported that TSMC plans to raise the order quotes for advanced process technologies and advanced packaging in 2025, among which the 3nm quote will increase by more than 5%. The specific situation depends on the quantity of orders and the terms of the agreement, and the current wafer quote is more than $20,000. The quote for CoWoS packaging will increase by 10%-20%. It is rumored that TSMC's 3nm price increase plan has been agreed upon by customers, and both parties have reached a new agreement to ensure stable supply.
In addition, some industry insiders have revealed that the 4nm/5nm process technology for high-performance computing customers may increase by 11%, which means that the price of 4nm wafers will increase from $18,000 to about $20,000, an increase of at least 25% compared to the 2021 quote.
TSMC's 3nm, 4nm, and 5nm processes are all expected to increase in price, which indirectly indicates Samsung's predicament in these process markets. This is because only these two companies can provide mass production foundry capacity for the corresponding process technologies globally. In order to catch up with TSMC, Samsung has been promoting at low prices for many years since the mass production of the 7nm process, especially the most advanced 3nm process technology, which is much less than TSMC's quote. Now, the competitor's capacity is in short supply and still needs to increase prices, indicating that Samsung's 3nm customer orders are very few, and TSMC has the confidence to raise prices.
In summary, in terms of the most advanced processes that have been mass-produced, TSMC has a clear advantage, and Samsung's competitiveness in this area is difficult to catch up, and can only hope for the 2nm process.
03
TSMC wants a share of the HBM market
In early July, according to South Korean media reports, SK Hynix will deepen cooperation with TSMC and Nvidia, and announce a closer cooperation plan among the three companies at the International Semiconductor Exhibition (Semicon Taiwan) in September.
In 2022, TSMC announced the establishment of the OIP 3DFabric Alliance at the North American Technology Forum, incorporating memory and substrate partners. At that time, Kangwook Lee, Senior Vice President and Head of PKG Development at SK Hynix, revealed that the company has been closely cooperating with TSMC in the previous generations and current HBM technology to support the compatibility of CoWoS process and the interconnectivity of HBM. After joining the 3DFabric Alliance, SK Hynix will provide solutions for future HBM products (HBM4) through deeper cooperation with TSMC.According to South Korean media reports, industry insiders have said that SK Hynix CEO Kim Joo-sun will deliver a keynote speech at the International Semiconductor Exhibition to be held in Taipei in September. This will be the first time SK Hynix has participated in a keynote speech. After the speech, Kim Joo-sun will meet with senior executives of TSMC to discuss the next generation of HBM cooperation plans. Nvidia CEO Huang Renxun may also join the talks to further consolidate the tripartite alliance between SK Hynix, TSMC, and Nvidia.
It is reported that the cooperation among the three giants was finalized in the first half of 2024. In April, SK Group Chairman Choi Tae-won met with Huang Renxun to discuss semiconductor cooperation. In June, Choi Tae-won visited the newly appointed chairman of TSMC, Wei Zhejia, to further promote subsequent cooperation.
SK Hynix will use TSMC's logic process to produce the base interface chip of HBM. The report said that SK Hynix and TSMC have agreed to cooperate in the development and production of HBM4, which will be mass-produced in 2026.
HBM stacks the core chip on top of the base interface chip, connecting them vertically to each other. The HBM3E product produced by SK Hynix uses a base interface chip made by its own process technology, but starting from HBM4, it will use TSMC's advanced logic process. The report said that SK Hynix will introduce the results of the cooperation at the forum, and it is known that the power consumption of HBM4 is more than 20% lower than the original target.
Since the launch and mass production of HBM, SK Hynix has always been the exclusive supplier for Nvidia to equip its AI GPU with this type of memory. It is still the case for the HBM3E version, but starting from the second quarter of 2024, two other major memory manufacturers, Samsung and Micron, have joined the Nvidia HBM supply chain. These two memory giants are preparing to spend tens of billions of dollars to expand their HBM chip production capacity.
Not long ago, Samsung launched its 12-layer stacked HBM3E, challenging the industry status of SK Hynix's 8-layer stacked product. A senior executive of Samsung said that the company plans to double the chip output this year. In the face of competition, SK Hynix's HBM project is accelerating, and it is expected that the first batch of 12-layer stacked next-generation HBM4 will arrive in the second half of 2025 at the earliest, and there will be a 16-layer stacked product in 2026, which will develop towards a more customized direction.
The competition in the HBM3E market has already fallen behind, and hopes are on HBM4. Samsung is accelerating its research and development to narrow the gap with SK Hynix. In terms of the sixth-generation HBM chip HBM4, codenamed "Snowbolt," Samsung plans to apply buffer chips to the bottom layer of the stacked memory to improve efficiency.
While Samsung is catching up with its storage chip competitor SK Hynix, the latter is deepening cooperation with Samsung's wafer foundry "archenemy" TSMC. For Samsung, this is obviously bad news.
In mid-May, at the 2024 European Technology Seminar, TSMC said it would use its 12FFC+ (12nm level) and N5 (5nm level) process technologies to manufacture HBM4 interface chips.
The senior director of TSMC's design and technology platform said: "We are working with major HBM memory partners to develop advanced processes for full-stack integration of HBM4. The N5 process can provide more logic functions for HBM4 with lower power consumption." It is reported that the N5 process allows more logic functions to be packaged into HBM4 and achieves very fine interconnection spacing, which is crucial for direct bonding on logic chips and can improve the memory performance of AI and HPC processors.Compared to N5, TSMC's 12FFC+ process is more economical, with the base chips manufactured capable of building 12-layer and 16-layer HBM4 stacks, providing 48GB and 64GB of capacity respectively.
TSMC is also optimizing packaging technologies, especially CoWoS-L and CoWoS-R, to support HBM4 integration. These advanced packaging technologies help assemble 12-layer HBM4 memory stacks. According to TSMC, the experimental HBM4 memory has achieved a data transfer rate of 6 GT/s at 14mA.
TSMC's advanced process technology capabilities, along with SK Hynix's advanced memory chip manufacturing capabilities, can decompose the manufacturing of more complex HBM4 memory, leverage their respective advantages, and produce the best logic interfaces and DRAM wafers. Then, they can be assembled using advanced packaging technologies to maximize the performance advantages of this type of memory.
For Samsung, being suppressed by TSMC in the advanced process wafer foundry market, but as a leader in memory chips, Samsung is still very confident. Now, TSMC is deeply cooperating with its main competitor SK Hynix in the memory field, which is almost cutting off Samsung's retreat. To develop HBM4, it is unavoidable to have advanced logic chip process technology. If Samsung's wafer foundry business cannot do these well in the short term, it may also be inevitable to choose to cooperate with TSMC.
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